Guaranteeing Forward Progress of Unified Register Allocation and Instruction Scheduling

Increasingly demanding computation requirements and tighter energy constraints have motivated distributed and/or hierarchical register file (dhrf) organizations as a mean to efficiently sustain a sufficient alu utilization in processors targeting embedded applications with many alus. Compared to conventional centralized register file organizations, dhrfs lead to tighter coupling between register allocation and instruction scheduling: since latencies to register files are non-uniform, register allocation affects access latencies, thus in turn affects instruction scheduling. To avoid this phase order-